Dr.-Ing. Steffen Vaas

2021

• Vaas S., Ulbrich P., Eichler C., Wägemann P., Reichenbach M., Fey D.:
  Taming Non-Deterministic Low-Level I/O: Predictable Multi-Core Real-Time Systems by SoC Co-Design
  2021 IEEE 24th International Symposium on Real-Time Distributed Computing (ISORC)
  DOI: 10.1109/isorc52013.2021.00017
  URL: https://www4.cs.fau.de/Publications/2021/vaas_21_isorc.pdf

2019

• Bauer W., Holzinger P., Reichenbach M., Vaas S., Hartke P., Fey D.:
  Programmable HSA Accelerators for Zynq UltraScale+ MPSoC Systems
  Euro-Par 2018: Parallel Processing Workshops - Euro-Par 2018 International Workshops
  In: Mencagli G, B. Heras D, Cardellini V, Casalicchio E, Jeannot E, Wolf F, Salis A, Schifanella C, Manumachu RR, Ricci L, Beccuti M, Antonelli L, Garcia Sanchez JD, Scott SL (Hrsg.): Euro-Par 2018: Parallel Processing Workshops, Cham: 2019
  DOI: 10.1007/978-3-030-10549-5_57
• Häublein K., Brückner W., Vaas S., Rachuj S., Reichenbach M., Fey D.:
  Utilizing PYNQ for Accelerating Image Processing Functions in ADAS Applications
  ARCS 2019: 32nd International Conference on Architecture of Computing Systems (Copenhagen, 20. Mai 2019 - 24. Juni 2019)
• Vaas S., Ulbrich P., Reichenbach M., Fey D.:
  Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands
  In: Journal of Signal Processing Systems (2019)
  ISSN: 1939-8018
  DOI: 10.1007/s11265-018-1389-0

2018

• Rachuj S., Reichenbach M., Vaas S., Fey D.:
  Autonomous Driving in the Curriculum of Computer Architecture
  12th European Workshop on Microelectronics Education (Braunschweig, 24. September 2018 - 26. September 2018)
  In: Proceedings of the 12th European Workshop on Microelectronics Education 2018
  DOI: 10.1109/ewme.2018.8629484
• Reichenbach M., Liebischer L., Vaas S., Fey D.:
  Comparison of Lane Detection Algorithms for ADAS using Embedded Hardware Architectures
  Conference on Design and Architectures for Signal and Image Processing (DASIP) (Porto, 9. Oktober 2018 - 12. Oktober 2018)
  In: Proceedings of 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP), Porto: 2018
  DOI: 10.1109/DASIP.2018.8596994

2017

• Lieske T., Pfundt B., Vaas S., Reichenbach M., Fey D.:
  System on Chip Generation for Multi-Sensor and Sensor Fusion Applications
  17th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (Island of Samos, Greece)
  In: Proceedings of the 17th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2017
  DOI: 10.1109/SAMOS.2017.8344607
  URL: https://ieeexplore.ieee.org/document/8344607/
• Vaas S., Ulbrich P., Reichenbach M., Fey D.:
  The Best of Both: High-performance and Deterministic Real-Time Executive by Application-Specific Multi-Core SoCs
  Conference on Design and Architectures for Signal and Image Processing (DASIP '17) (Dresden, 27. September 2017 - 29. September 2017)
  In: Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP '17), Los Alamitos, CA: 2017
  DOI: 10.1109/DASIP.2017.8122107

2016

• Vaas S., Reichenbach M., Fey D.:
  An Application-Specific Instruction Set Processor for Power Quality Monitoring
  23th Reconfigurable Architectures Workshop (RAW) (Chicago, 23. Mai 2016 - 27. Mai 2016)
  In: Parallel and Distributed Processing Symposium Workshop (IPDPSW) 2016
  DOI: 10.1109/IPDPSW.2016.143
• Vaas S., Reichenbach M., Hofmann J., Stadelmayer T., Fey D.:
  Embedded Parallel Computing Accelerators for Smart Control Units of Frequency Converters
  12th Workshop on Parallel Systems and Algorithms (PASA) (Nuremberg, 4. April 2016 - 7. April 2016)
  In: ARCS 2016; 29th International Conference on Architecture of Computing Systems, Nuremberg, Germany: 2016
• Vaas S., Reichenbach M., Margull U., Fey D.:
  The R2-D2 Toolchain - Automated Porting of Safety-Critical Applications to FPGAs
  2016 International Conference on ReConFigurable Computing and FPGAs (Cancun, 30. November 2016 - 2. Dezember 2016)
  In: Proceedings of ReConFig' 16 2016
  DOI: 10.1109/ReConFig.2016.7857192
  URL: http://ieeexplore.ieee.org/document/7857192/

2015

• Reichenbach M., Lieske T., Vaas S., Häublein K., Fey D.:
  FAUPU - A Design Framework for the Development of Programmable Image Processing Architectures
  2015 International Conference on ReConFigurable Computing and FPGAs (Mayan Riveria, Mexico)
  In: Proceedings of ReConFig' 15 2015
  DOI: 10.1109/ReConFig.2015.7393309