Farhad EbrahimiAzandaryani
Farhad Ebrahimi Azandaryani, M. Sc.
Department Informatik (INF)
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Martensstr. 3
91058 Erlangen
Profile Info
Farhad EbrahimiAzandaryani holds an M.Sc. degree in computer engineering, specializing in Computer Architecture, Approximate Computing, and Energy-Efficient Low-Power Design from the University of Tehran, Iran, in 2019. Since 2022, he has served as a lecturer and research assistant at Friedrich-Alexander-Universität Erlangen-Nuremberg (FAU), focusing on improving RISC-V processor performance using Ternary Encoding and hardware accelerators. he also has experience in designing FPGA-based RISC-V processors, including both bare-metal and Petalinux-initiated configurations on various 7-series and Ultrascale+ family platforms.
Projects and Research Interests
- Hardware development with FPGAs
- Approximate and reconfigurable computing
- Non-volatile ternary processors based on the free processor instruction set architecture RISC-V
Teaching
- Architecture of Supercomputers (ArchSup) Winter 2022/23 – ongoing
- Computer Architecture for Medical Applications (CAMA) Summer 2023 – ongoing
Publications
- F. EbrahimiAzandaryani and D. Fey, “ ExTern: Boosting RISC-V core performance using ternary encoding ”
Microprocessors and Microsystems , volume 107(2024), https://doi.org/10.1016/j.micpro.2024.105058. - F. Ebrahimi-Azandaryani , O. Akbari, M. Kamal, A. Afzali-Kusha, and M. Pedram, “ Accuracy configurable adders with negligible delay overhead in exact operating mode ”
ACM Trans. Des. Autom. Electron. Syst ., vol. 28, no. 1, pp. 1–14, Jan. 2023. - F. Ebrahimi-Azandaryani , O. Akbari, M. Kamal, A. Afzali-Kusha, and M. Pedram, “ Block-based carry speculative approximate adder for energy-efficient applications, ”
IEEE Trans. Circuits Syst. II , Exp. Briefs, vol. 67, no. 1, pp. 137–141, Jan. 2019.