Farhad Ebrahimi Azandaryani

Profile Information

I’m Farhad EbrahimiAzandaryani and I hold a B.Sc. in computer architecture from Hamedan University of Technology (HUT) since 2015. I earned my M.Sc. in computer engineering, specializing in Computer Architecture, Approximate computing, and Energy Efficient Low Power design from the University of Tehran, Iran, in 2019. Since 2022, I have held positions as a Lecturer and Research Assistant at Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), concentrating on enhancing RISC-V processor performance through computer arithmetic approaches like Ternary Encoding and hardware accelerators. Furthermore, I have delved into designing FPGA-based RISC-V processors across various design environments and System-on-Chip (SoC) configurations. This includes bare-metal designs as well as initiating Petalinux with an Ubuntu root filesystem for development on the Ultrascale+ family to facilitate communication and monitoring with the PL IP core.

Projects

• Non-volatile ternary processors based on the free processor instruction set architecture RISC-V

Teaching

• Architecture of Supercomputers (ArchSup) Winter 2022/23 – ongoing
• Computer Architecture for Medical Applications (CAMA) Summer 2023 – ongoing

Publications

• F. EbrahimiAzandaryani and D. Fey, „ ExTern: Boosting RISC-V core performance using ternary encoding,„
  Microprocessors and Microsystems , volume 107(2024), https://doi.org/10.1016/j.micpro.2024.105058.
• F. Ebrahimi-Azandaryani , O. Akbari, M. Kamal, A. Afzali-Kusha, and M. Pedram, “ Accuracy configurable adders with negligible delay overhead in exact operating mode ,”
  ACM Trans. Des. Autom. Electron. Syst ., vol. 28, no. 1, pp. 1–14, Jan. 2023.
• F. Ebrahimi-Azandaryani , O. Akbari, M. Kamal, A. Afzali-Kusha, and M. Pedram, “ Block-based carry speculative approximate adder for energy-efficient applications ,”
  IEEE Trans. Circuits Syst. II , Exp. Briefs, vol. 67, no. 1, pp. 137–141, Jan. 2019.