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John Reuben

Post-doctoral researcher

Department of Computer Science
Chair of Computer Science 3 (Hardware Architectures)

Raum: Raum 07.139
Martenstrasse 3
91058 Erlangen
Germany

Information

 

March 2018-present: Post-doctoral researcher at the Chair of Computer Architecture (Prof.Dietmar Fey)

at the Friedrich-Alexander-Universität Erlangen-Nürnberg

Jan 2017-Jan 2018: Post-doctoral researcher at ASIC2 group (Prof.Shahar Kvatinsky), Technion- Israel Institute of Technology

2015: PhD. in Electronic Design automation/CAD for VLSI  from VIT University, India 

Research Interests
  • Resistive RAMs and other memristive technologies (FeFET, PCM,MRAM)
  • In-memory computing, memristive logic
  • Beyond-CMOS computing

Open Projects (Bachelor’s/Masters)

(contact me if interested: johnreubenp@gmail.com)
  1. Design of Peripheral circuitry of Memory array for In-memory computing (Required skills: SPICE  transistor level simulation)
  2. Post-layout simulation of peripheral circuit (Read-out circuit) for multilevel memories (Required skills: layout level simulation; See IEEE NorCAS paper below)

Recent Publications (2019 –  )

[1] John Reuben, Dietmar Fey and Christian Wenger, „A Modeling Methodology for Resistive RAM Based on Stanford-PKU Model With Extended Multilevel Capability,“ in IEEE Transactions on Nanotechnology, vol. 18, pp. 647-656, 2019.    Modified Stanford-PKU model to simulate Multilevel SET process-> Download  CODE
doi: https://doi.org/10.1109/TNANO.2019.2922838

[2] . Talati, R. Ben Hur, N. Wald, A. Ali, John Reuben, and S. Kvatinsky, „mMPU – a Real Processing–in–Memory Architecture to Combat the von Neumann Bottleneck,“ Ed. Mannan Suri, Applications of Emerging Memory Technology. Springer Series in Advanced Microelectronics, vol 63. Springer, Singapore
doi: https://doi.org/10.1007/978-981-13-8379-3_8

[3]  John Reuben and Dietmar Fey, „A Time-based Sensing Scheme for Multilevel Cell (MLC) Resistive RAM,“ in IEEE Nordic Circuits And Systems Conference (NORCAS), Finland, October 2019.

doi: https://opus4.kobv.de/opus4-fau/frontdoor/index/index/docId/12321

[4] John Reuben, R. Ben-Hur, N. Wald, N. Talati, A.Ali, P.-E. Gaillardon, and S. Kvatinsky, “A taxonomy and evaluation framework for memristive logic,” in Handbook of Memristor Networks, A. Adamatzky, L. Chua, and G. Sirakoulis, Eds. Springer International Publishing, 2019.

doi: https://doi.org/10.1007/978-3-319-76375-0_37