# John Reuben, Ph.D.

## John Reuben Prabahar, Ph.D.

### Information

Received ETI funding in 2020: **EUR 12,000** to do preliminary research to apply for DFG grant.

**March 2018-present** : Post-doctoral researcher at the Chair of Computer Architecture ( **Prof. Dietmar Fey** )

at Chair of Computer Architecture, *Friedrich-Alexander University Erlangen-Nuremberg*

**Jan 2017-Jan 2018** : Post-doctoral researcher at ASIC2 group ( **Prof. Shahar Kvatinsky** ), Technion- Israel Institute of Technology (Viterbi Postdoc fellowship)

**2015** : Ph.D. in Electronic Design Automation / CAD for VLSI from VIT University, Vellore, India.

### Research Interests

- Resistive RAMs, ferroelectric memories (FTJ, FeFET) and other memristive technologies (PCM, MRAM)
- In-memory computing, memristive logic, in-memory arithmetic
- Beyond CMOS computing

Note: The following list is **selected** publication list. See Google Scholar , Scopus profile for the complete publication list.

**KEY PUBLICATIONS:**

1. V. Lakshmi, V. Pudi and **John Reuben**, “Inner Product Computation In-Memory Using Distributed Arithmetic,” in ** IEEE Transactions on Circuits and Systems I: Regular Papers**, vol. 69, no. 11, pp. 4546-4557, Nov. 2022, doi: 10.1109/TCSI.2022.3193678

2. V. Lakshmi,

**John Reuben**, and V. Pudi, “A novel in-memory wallace tree multiplier architecture using majority logic,”

*, vol. 69, no. 3, pp. 1148-1158, March 2022. doi: 10.1109/TCSI.2021.3129827*

**IEEE Transactions on Circuits and Systems I: Regular Papers**3.

**John Reuben**and S. Pechmann, “Accelerated addition in resistive ram array using parallel-friendly majority gates,”

*, vol. 29, no. 6, pp. 1108–1121, 2021. doi: 10.1109/TVLSI.2021.3068470 (See preliminary version of this research in*

**IEEE Transactions on Very Large Scale Integration (VLSI) Systems****ASAP**

**conference presentation video**here (20 min) conference presentation video)

4.

**John Reuben**, M. Biglari and D. Fey, “Incorporating Variability of Resistive RAM in Circuit Simulations using the Stanford–PKU Model”,

*, vol. 19, pp. 508-518, 2020. doi:*

**IEEE Transactions on Nanotechnology**10.1109/TNANO.2020.3004666

5.

**John Reuben**, D. Fey and C. Wenger, “A Modeling Methodology for Resistive RAM Based on Stanford-PKU Model With Extended Multilevel Capability,”

*, vol. 18, pp. 647-656, 2019. doi: 10.1109/TNANO.2019.2922838*

**IEEE Transactions on Nanotechnology****VIDEO LECTURES:**

I taught „**CAD for VLSI/ Electronic Design automation course**“ for Masters Program in VLSI at VIT university, India. During those years (2012-2016), I prepared a series of video lectures elucidating some classical algorithms used for physical design automation. They are available on youtube for public access. The links to those video lectures are below:

(Note: Animations in my videos were made by Mr.Sanket Yawalker(Masters in VLSI design, 2014 batch. His contribution is acknowledged.)

- Clock Distribution network- Introduction : In this lecture, I give an introduction to one of the crucial aspects of physical design- the clock distribution network.
- Exact zero skew clock routing algorithm: The exact zero skew clock routing algorithm, proposed by Tsay in 1993 is still used in many clock tree synthesis tools. This algorithm is foundational to all the latest developments in clock distribution. This lecture presents the algorithm with an example.
- Introduction to floor planning : In this lecture, I give an introduction to floor planning – the phase in physical design flow after partitioning where the modules are assigned a tentative location on the chip. Includes an interesting animation on slicing tree to represent a floor plan.
- Floor planning by Polish expression (Wong-Liu algorithm): The polish expression, proposed by Wong and Liu is a succinct representation of slicing floor plans. In this lecture, I explain how floor plans can be represented by polish expressions and how simulated annealing can be used to optimize the floor plan. I also discuss an example from the book „Practical problems in VLSI PDA“ by Prof. Sung Kyu Lim, Georgia Tech
- Floor planning by Polish expression- contd : The continuation of my previous lecture on floor planning using polish expression. The 3 moves suggested by Wong and Liu are illustrated by animation.
- Introduction to Partitioning

In this lecture, I give an introduction to the first step in physical design automation of integrated circuit. - Kernighan-Lin(KL) algorithm for partitioning

KL algorithm is an iterative improvement algorithm for bi-partitioning a netlist.Belonging to the class of group migration algorithms, it is based on exchanging a pair of nodes across the partition to reduce the cutset this lecture, the algorithm is explained with an example. - Floorplanning by Integer Linear Programming(ILP) Integer Linear Programming(ILP) is a general optimization technique. In this algorithm the floor planning problem in VLSI physical design is formulated as an ILP and solved.
- Placement- Sequence pair representation: The sequence pair is a concise representation of non-slicing floor plan. In this lecture, I introduce sequence pair representation and illustrate how it can be used together with simulated annealing for optimization in VLSI placement. I also discuss an example from the book „Practical problems in VLSI PDA“ by Prof. Sung Kyu Lim, Georgia Tech
- Channel routing- Left Edge and Dogleg Algorithm: In this lecture, the left edge algorithm for Channel routing is described. The dogleg algorithm, which improves the left edge algorithm by net-splitting is also discussed.
- Clock Mesh In this lecture, I discuss mesh based clock distribution method which has received much attention since 2010. Clock mesh is more resistant to on chip variations when compared to tree, but this achieved at cost of more power.

**Digital IC design Lab for Masters‘ in VLSI program**

(Voice in the following 2 demos is of Dr.Mohammed Zackriya, VIT University)

Layout of Inverter – Part -I

In this lab demo, we show how to draw the layout of a CMOS inverter using Cadence Virtuoso, Technology-90 nm

Layout of Inverter – Part -II

In this lab demo, we show how to post layout simulation of a CMOS inverter using Cadence Virtuoso, Technology-90 nm

**Analog Electronics Lab **

Introduction to lab equipment and Common Emitter(CE) amplifier (FG, Oscilloscope and voltage regulator)

Frequency response of CE amplifier