John Reuben, Ph.D.

John Reuben Prabahar, Ph.D.

Post-doctoral researcher

Department of Computer Science
Chair of Computer Science 3 (Hardware Architectures)

Raum: Raum 07.139
Martenstrasse 3
91058 Erlangen
Germany

information

Received ETI funding : EUR 12,000 to do preliminary research to apply for DFG grant.

March 2018-present : Post-doctoral researcher at the Chair of Computer Architecture ( Prof. Dietmar Fey )

at the Friedrich-Alexander University Erlangen-Nuremberg

Jan 2017-Jan 2018 : Post-doctoral researcher at ASIC2 group ( Prof. Shahar Kvatinsky ), Technion- Israel Institute of Technology

2015 : PhD. in Electronic Design automation / CAD for VLSI from

Research Interests
  • Resistive RAMs and other memristive technologies (PCM, MRAM)
  • In-memory computing, memristive logic
  • Beyond CMOS computing

Open Projects (Bachelor’s / Masters / Aspiring doctoral students )

(contact me if interested: johnreubenp@gmail.com

I am looking for a student to do the physical design of the memory array (with read-out circuit / sense amplifier) ​​for a test chip to demonstrate in-memory majority gate (Required skills: Physical design / Schematic driven layout). Student research assistant (Hiwi) will be paid according to FAU norms.

Recent Publications (2019 -)

[12]  John Reuben and Dietmar Fey “ Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles ”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI) , July 2021 (Tampa, Florida)

[11] John Reuben and S. Pechmann, “ Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates ,“ in  IEEE Transactions on Very Large Scale Integration (VLSI) Systems , doi: 10.1109 / TVLSI.2021.3068470 10.1109 / TVLSI.2021.3068470 . See video

[10] Pérez-Bosch Quesada, Emilio; Romero-Zaliz, Rocío; Perez, Eduardo; Kalishettyhalli Mahadevaiah, Mamathamba; Reuben, John ; Schubert, Markus A .; Jiménez-Molinos, Francisco; Roldan, Juan B .; Wenger, Christian. 2021. “ Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems “  Electronics 10, no. 6: 645. doi: 10.3390 / electronics10060645

[9] D. Fey and John Reuben , „ Direct state transfer in MLC based memristive ReRAM devices for ternary computing “, 2020 European Conference on Circuit Theory and Design (ECCTD) , Sofia, Bulgaria, 2020, pp. 1-5 , doi: 10.1109 / ECCTD49232.2020.9218323 .

[8]  John Reuben, „ Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing “. J. Low Power Electron. Appl.  202010 , 28. doi:  10.3390 / jlpea10030028

[7]. John Reuben , M. Biglari and D. Fey, „ Incorporating Variability of Resistive RAM in Circuit Simulations using the Stanford – PKU Model „, IEEE Transactions on Nanotechnology , vol. 19, pp. 508-518, 2020. doi: 10.1109 / TNANO.2020.3004666

[6] John Reuben , S. Pechmann, „ A Parallel-friendly Majority Gate to Accelerate In-memory Computation, “ in IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) , Manchester, UK, 2020, pp. 1-8. doi:  10.1109 / ASAP49362.2020.00025

See conference presentation video here (20 min) conference presentation video

[5] John Reuben , „ Binary addition in resistance switching memory array by sensing majority, „in Micromachines , vol. 11, No. 5, 2020. doi: 10.3390 / mi11050496

[4] John Reuben , Dietmar Fey and Christian Wenger, „ A Modeling Methodology for Resistive RAM Based on Stanford-PKU Model With Extended Multilevel Capability , „in IEEE Transactions on Nanotechnology , vol. 18, pp. 647-656, 2019.    Modified Stanford-PKU model to simulate Multilevel SET process-> Download CODE doi: https://doi.org/10.1109/TNANO.2019.2922838 

[3]. Talati, R. Ben Hur, N. Wald, A. Ali, John Reuben, and S. Kvatinsky, “ mMPU – a Real Processing-in-Memory Architecture to Combat the von Neumann Bottleneck ,“ Ed. Mannan Suri, Applications of Emerging Memory Technology . Springer Series in Advanced Microelectronics, vol 63.Springer, Singapore
doi: https://doi.org/10.1007/978-981-13-8379-3_8

[2]  John Reuben and Dietmar Fey, „ A Time-based Sensing Scheme for Multilevel Cell (MLC) Resistive RAM , „in IEEE Nordic Circuits And Systems Conference (NORCAS) , Finland, October 2019. doi: 10.1109 / NORCHIP.2019.8906921 

[1] John Reuben , R. Ben-Hur, N. Wald, N. Talati, A.Ali, P.-E. Gaillardon, and S. Kvatinsky, “ A taxonomy and evaluation framework for memristive logic ,“ in Handbook of Memristor Networks , A. Adamatzky, L. Chua, and G. Sirakoulis, Eds. Springer International Publishing, 2019. doi: https://doi.org/10.1007/978-3-319-76375-0_37