Philipp Holzinger

Philipp Holzinger, M. Sc.

Department Informatik (INF)
Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Raum 07.159
Martensstraße 3
91058 Erlangen

Telefon: +49 9131 85 27010
Faxnummer: +49 9131 85 27912
E-Mail: philipp.holzinger@fau.de
Webseite: http://www3.cs.fau.de/blog/person/philipp-holzinger/

Information

Since November 2017, Philipp Holzinger is a member of the research staff at the Chair of Computer Architecture. He holds a Master’s Degree (M.Sc.) in Computer Science.

Research Interests

Heterogeneous System Architecture
Hardware Development with FPGAs
High Level Synthesis
Architectures for Deep Learning

Publications

2021

Holzinger P., Reichenbach M.:
The HERA Methodology: Reconfigurable Logic in General-Purpose Computing
In: IEEE Access 9 (2021), S. 147212-147236
ISSN: 2169-3536
DOI: 10.1109/ACCESS.2021.3123874
Holzinger P., Reiser D., Hahn T., Reichenbach M.:
Fast HBM Access with FPGAs: Analysis, Architectures, and Applications
IEEE International Parallel and Distributed Processing Symposium Workshops (Virtual.)
Pfenning S., Holzinger P., Reichenbach M.:
Transparent FPGA Acceleration with TensorFlow
DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021) (Virtual.)

2019

Ali R., Mallah M., Leyh M., Holzinger P., Breiling M., Reichenbach M., Fey D.:
A Hardware Inference Accelerator for Temporal Convolutional Networks
2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) (Helsinki, 29. Oktober 2019 - 30. Oktober 2019)
In: IEEE (Hrsg.): Proceedings of Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2019 IEEE 2019
DOI: 10.1109/NORCHIP.2019.8906963
URL: https://ieeexplore.ieee.org/document/8906963
Bauer W., Holzinger P., Rachuj S., Häublein K., Reichenbach M., Fey D.:
Evaluating HSA-Compatible Heterogeneous Systems for ADAS Applications
ARCS 2019: 32nd International Conference on Architecture of Computing Systems (Copenhagen, Denmark, 20. Mai 2019 - 24. Mai 2019)
In: Trinitis, Carsten; Pionteck, Thilo (Hrsg.): Workshop Proceedings 2019
Bauer W., Holzinger P., Reichenbach M., Vaas S., Hartke P., Fey D.:
Programmable HSA Accelerators for Zynq UltraScale+ MPSoC Systems
Euro-Par 2018: Parallel Processing Workshops - Euro-Par 2018 International Workshops
In: Mencagli G, B. Heras D, Cardellini V, Casalicchio E, Jeannot E, Wolf F, Salis A, Schifanella C, Manumachu RR, Ricci L, Beccuti M, Antonelli L, Garcia Sanchez JD, Scott SL (Hrsg.): Euro-Par 2018: Parallel Processing Workshops, Cham: 2019
DOI: 10.1007/978-3-030-10549-5_57

2018

Holzinger P., Reichenbach M., Fey D.:
A New Generic HLS Approach for Heterogeneous Computing: On the Feasibility of High-Level Synthesis in HSA-Compatible Systems
SAMOS XVIII: 2018 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (Pythagorion, Samos Island, 15. Juli 2018 - 19. Juli 2018)
In: Mudge Trevor, Pnevmatikatos Dionisios N. (Hrsg.): SAMOS XVIII: 2018 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, New York, NY, USA: 2018
DOI: 10.1145/3229631.3229634
URL: https://dl.acm.org/citation.cfm?doid=3229631.3229634
Reichenbach M., Holzinger P., Häublein K., Lieske T., Blinzer P., Fey D.:
Heterogeneous Computing Utilizing FPGAs
In: Journal of Signal Processing Systems 91 (2018), S. 745--757
ISSN: 1939-8018
DOI: 10.1007/s11265-018-1382-7

2017

Reichenbach M., Holzinger P., Häublein K., Lieske T., Blinzer P., Fey D.:
LibHSA: One Step Towards Mastering the Era of Heterogeneous Hardware Accelerators using FPGAs
2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)
DOI: 10.1109/DASIP.2017.8122108