Prof. Dr.-Ing. Dietmar Fey

Prof. Dr.-Ing. Dietmar Fey

Department Informatik (INF)
Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Raum: Raum 07.156
Martensstr. 3
91058 Erlangen

Sprechzeiten

nach Vereinbarung

2025

  • , :
    CSD-Driven Speedup in RISC-V Processor
    18th International Workshop on Design and Architecture for Signal and Image Processing, DASIP 2025 (Barcelona, 20. Januar 2025 - 22. Januar 2025)
    In: Design and Architecture for Signal and Image Processing. 18th International Workshop, DASIP 2025, Barcelona, Spain, January 20–22, 2025, Proceedings, Cham:
    DOI: 10.1007/978-3-031-87897-8_1
  • , , , , , , , , , , , :
    RISC-V CPU Design Using RRAM-CMOS Standard Cells
    In: IEEE Transactions on Very Large Scale Integration (Vlsi) Systems ()
    ISSN: 1063-8210
    DOI: 10.1109/TVLSI.2025.3554476

2024

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1998