Prof. Dr.-Ing. Dietmar Fey

Department Informatik (INF)
Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Raum 07.156
Martensstrasse 3
91058 Erlangen

Telefon: +49 9131 85 27003
Faxnummer: +49 9131 85 27912
E-Mail: dietmar.fey@informatik.uni-erlangen.de
Webseite: http://www3.informatik.uni-erlangen.de/persons/fey/

Sprechzeiten

nach Vereinbarung

Ringlein B., Abel F., Ditter A., Weiss B., Hagleitner C., Fey D.:
ZRLMPI: A Unified Programming Model for Reconfigurable Heterogeneous Computing Clusters
28th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2020 (Fayetteville, AR, 3. Mai 2020 - 6. Mai 2020)
In: Proceedings - 28th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2020 2020
DOI: 10.1109/FCCM48280.2020.00051
Fey D., Karl W., Ungerer T.:
Memristoren für zukünftige Rechnersysteme
In: Informatik-Spektrum (2020)
ISSN: 0170-6012
DOI: 10.1007/s00287-020-01261-8
Jordan H., Gschwandtner P., Thoman P., Zangerl P., Hirsch A., Fahringer T., Heller T., Fey D.:
The allscale framework architecture
In: Parallel Computing (2020), Art.Nr.: 102648
ISSN: 0167-8191
DOI: 10.1016/j.parco.2020.102648
Fritscher M., Knödtel J., Reichenbach M., Fey D.:
Simulating memristive systems in mixed-signal mode using commercial design tools
26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 (Genoa, 27. November 2019 - 29. November 2019)
In: 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 2019
DOI: 10.1109/ICECS46596.2019.8964856
Ali R., Mallah M., Leyh M., Holzinger P., Breiling M., Reichenbach M., Fey D.:
A Hardware Inference Accelerator for Temporal Convolutional Networks
2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) (Helsinki, 29. Oktober 2019 - 30. Oktober 2019)
In: IEEE (Hrsg.): Proceedings of Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2019 IEEE 2019
DOI: 10.1109/NORCHIP.2019.8906963
URL: https://ieeexplore.ieee.org/document/8906963
Reuben JR., Fey D.:
A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM
5th IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 (Helsinki, 29. Oktober 2019 - 30. Oktober 2019)
In: Jari Nurmi, Peeter Ellervee, Kari Halonen, Juha Roning (Hrsg.): 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings 2019
DOI: 10.1109/NORCHIP.2019.8906921
Ringlein B., Abel F., Ditter A., Weiss B., Hagleitner C., Fey D.:
System architecture for network-attached FPGAs in the cloud using partial reconfiguration
29th International Conferenceon Field-Programmable Logic and Applications, FPL 2019 (Barcelona, 9. September 2019 - 13. September 2019)
In: Ioannis Sourdis, Christos-Savvas Bouganis, Carlos Alvarez, Leonel Antonio Toledo Diaz, Pedro Valero, Xavier Martorell (Hrsg.): Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019 2019
DOI: 10.1109/FPL.2019.00054
Ditter A., Tielemann M., Fey D.:
Bridging the gap between high-performance, cloud and service-oriented computing
4th IEEE International Workshops on Foundations and Applications of Self* Systems, FAS*W 2019 (Umea, SWE, 16. Juni 2019 - 20. Juni 2019)
In: Proceedings - 2019 IEEE 4th International Workshops on Foundations and Applications of Self* Systems, FAS*W 2019 2019
DOI: 10.1109/FAS-W.2019.00029
Bauer W., Holzinger P., Reichenbach M., Vaas S., Hartke P., Fey D.:
Programmable HSA Accelerators for Zynq UltraScale+ MPSoC Systems
Euro-Par 2018: Parallel Processing Workshops - Euro-Par 2018 International Workshops
In: Mencagli G, B. Heras D, Cardellini V, Casalicchio E, Jeannot E, Wolf F, Salis A, Schifanella C, Manumachu RR, Ricci L, Beccuti M, Antonelli L, Garcia Sanchez JD, Scott SL (Hrsg.): Euro-Par 2018: Parallel Processing Workshops, Cham: 2019
DOI: 10.1007/978-3-030-10549-5_57
Bauer W., Holzinger P., Rachuj S., Häublein K., Reichenbach M., Fey D.:
Evaluating HSA-Compatible Heterogeneous Systems for ADAS Applications
ARCS 2019: 32nd International Conference on Architecture of Computing Systems (Copenhagen, Denmark, 20. Mai 2019 - 24. Mai 2019)
In: Trinitis, Carsten; Pionteck, Thilo (Hrsg.): Workshop Proceedings 2019
Biglari M., Lieske T., Fey D.:
Reducing Hibernation Energy and Degradation in Bipolar ReRAM-Based Non-Volatile Processors
In: IEEE Transactions on Nanotechnology (2019)
ISSN: 1536-125X
DOI: 10.1109/TNANO.2019.2922363
Häublein K., Brückner W., Vaas S., Rachuj S., Reichenbach M., Fey D.:
Utilizing PYNQ for Accelerating Image Processing Functions in ADAS Applications
ARCS 2019: 32nd International Conference on Architecture of Computing Systems (Copenhagen, 20. Mai 2019 - 24. Juni 2019)
Peschel J., Knödtel J., Pérez E., Reichenbach M., Wenger C., Fey D.:
Optimizing Multi-State Reliability in ReRAM Arrays using an Automated Device Selection Method
MEMRISYS 2019 International Conference on Memristive Materials, Devices & Systems (International Congress Center Dresden, 8. Juli 2019 - 11. Juli 2019)
Rachuj S., Reichenbach M., Fey D.:
A generic functional simulation of heterogeneous systems
32nd International Conference on Architecture of Computing Systems, ARCS 2019 (Copenhagen, 20. Mai 2019 - 23. Mai 2019)
In: Martin Schoeberl, Thilo Pionteck, Sascha Uhrig, Jürgen Brehm, Christian Hochberger (Hrsg.): Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2019
DOI: 10.1007/978-3-030-18656-2_10
Reuben JR., Fey D., Wenger C.:
A modeling methodology for resistive RAM based on stanford-PKU model with extended multilevel capability
In: IEEE Transactions on Nanotechnology 18 (2019), S. 647-656
ISSN: 1536-125X
DOI: 10.1109/TNANO.2019.2922838
Knödtel J., Schwabe W., Lieske T., Reichenbach M., Fey D.:
A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs
28th International Symposium on Power and Timing Modeling, Optimization and Simulation (Platja D’Aro, 2. Juli 2018 - 4. Juli 2018)
In: 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2018
DOI: 10.1109/PATMOS.2018.8464149
Schwarzmeier C., Ditter A., Fey D.:
Distributed Asynchronous Jacobi Methods
CoSaS 2018
International Symposium on Computational Science at Scale (Erlangen, 5. September 2018 - 7. September 2018)
Rachuj S., Reichenbach M., Vaas S., Fey D.:
Autonomous Driving in the Curriculum of Computer Architecture
12th European Workshop on Microelectronics Education (Braunschweig, 24. September 2018 - 26. September 2018)
In: Proceedings of the 12th European Workshop on Microelectronics Education 2018
Holzinger P., Reichenbach M., Fey D.:
A New Generic HLS Approach for Heterogeneous Computing: On the Feasibility of High-Level Synthesis in HSA-Compatible Systems
SAMOS XVIII: 2018 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (Pythagorion, Samos Island, 15. Juli 2018 - 19. Juli 2018)
In: Mudge Trevor, Pnevmatikatos Dionisios N. (Hrsg.): SAMOS XVIII: 2018 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, New York, NY, USA: 2018
DOI: 10.1145/3229631.3229634
URL: https://dl.acm.org/citation.cfm?doid=3229631.3229634
Rachuj S., Herglotz C., Reichenbach M., Kaup A., Fey D.:
A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Model
Architecture of Computing Systems – ARCS 2018 (Braunschweig, 9. April 2018 - 12. April 2018)
In: Mladen Berekovic, Rainer Buchty, Heiko Hamann, Dirk Koch, Thilo Pionteck (Hrsg.): 31st International Conference on Architecture of Computing Systems, ARCS 2018 2018
DOI: 10.1007/978-3-319-77610-1_7
URL: http://arcs2018.itec.kit.edu/
Fey D., Hannig F.:
Special Issue on Heterogeneous Real-Time Image Processing
In: Journal of Real-Time Image Processing 14 (2018), S. 513-515
ISSN: 1861-8200
DOI: 10.1007/s11554-018-0763-2
Wust D., Fey D., Knödtel J.:
A programmable ternary CPU using hybrid CMOS/memristor circuits
In: International Journal of Parallel, Emergent and Distributed Systems (2018), S. 1--21
ISSN: 1744-5760
DOI: 10.1080/17445760.2017.1422251
Vaas S., Ulbrich P., Reichenbach M., Fey D.:
Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands
In: Journal of Signal Processing Systems (2018)
ISSN: 1939-8018
Söll C., Reichenbach M., Röber J., Hagelauer A., Weigel R., Fey D.:
Case Study on Memristor-Based Multilevel Memories
In: International Journal of Circuit Theory and Applications 46 (2018), S. 99-112
ISSN: 0098-9886
DOI: 10.1002/cta.2379
Lieske T., Uhring W., Dumas N., Skilitsi AI., Leonard J., Fey D.:
Embedded Fluorescence Lifetime Determination for High-Throughput, Low-Photon-Number Applications
In: Journal of Signal Processing Systems (2018)
ISSN: 1939-8018
DOI: 10.1007/s11265-018-1372-9
URL: https://link.springer.com/article/10.1007/s11265-018-1372-9
Maliszewski AM., Griebler D., Schepke C., Ditter A., Fey D., Fernandes LG.:
The NAS Benchmark Kernels for Single and Multi-Tenant Cloud Instances with LXC/KVM
16th International Conference on High Performance Computing and Simulation, HPCS 2018 (Orléans, 16. Juli 2018 - 20. Juli 2018)
In: 2018 International Conference on High Performance Computing Simulation (HPCS) 2018
DOI: 10.1109/HPCS.2018.00066
Rachuj S., Bauer W., Fey D.:
Evaluation of a Sensor Fusion Algorithm on a Real-Time Processor
AmE 2018 - Automotive meets Electronics (Dortmund)
In: AmE 2018 - Automotive meets Electronics 2018
Hofmann J., Hager G., Fey D.:
On the Accuracy and Usefulness of Analytic Energy Models for Contemporary Multicore Processors
High Performance Computing: 33rd International Conference, ISC High Performance 2018 (Frankfurt, 24. Juni 2018 - 28. Juni 2018)
In: High Performance Computing: 33rd International Conference, ISC High Performance 2018, Cham: 2018
DOI: 10.1007/978-3-319-92040-5_2
Biglari M., Lieske T., Fey D.:
High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States
14th IEEE/ACM International Symposium on Nanoscale Architectures (Athens, Greece)
In: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, New York, NY, USA: 2018
DOI: 10.1145/3232195.3232217
URL: http://doi.acm.org/10.1145/3232195.3232217
Widerspick C., Bauer W., Fey D.:
Latency Measurements for an Emulation Platform on Autonomous Driving Platform NVIDIA Drive PX2
In: ARCS Workshop 2018; 31th International Conference on Architecture of Computing Systems 2018
Lieske T., Biglari M., Fey D.:
Multi-Level Memristive Voltage Divider: Programming Scheme Trade-offs
International Symposium on Memory Systems (MEMSYS) (Alexandria, Virginia, 1. Oktober 2018 - 4. Oktober 2018)
In: Proceedings of the International Symposium on Memory Systems, New York, NY, USA: 2018
DOI: 10.1145/3240302.3240430
URL: http://doi.acm.org/10.1145/3240302.3240430
Reichenbach M., Liebischer L., Vaas S., Fey D.:
Comparison of Lane Detection Algorithms for ADAS using Embedded Hardware Architectures
Conference on Design and Architectures for Signal and Image Processing (DASIP) (Porto, 9. Oktober 2018 - 12. Oktober 2018)
In: Proceedings of 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP), Porto: 2018
DOI: 10.1109/DASIP.2018.8596994
Reichenbach M., Holzinger P., Häublein K., Lieske T., Blinzer P., Fey D.:
Heterogeneous Computing Utilizing FPGAs
In: Journal of Signal Processing Systems (2018)
ISSN: 1939-8018
DOI: 10.1007/s11265-018-1382-7
Kuckuk S., Leitenmaier L., Schmitt C., Schönwetter D., Köstler H., Fey D.:
Towards Virtual Hardware Prototyping for Generated Geometric Multigrid Solvers
CS 2017-01 (2017), S. 1-8
ISSN: 2191-5008
Open Access: http://nbn-resolving.de/urn:nbn:de:bvb:29-opus4-83179
URL: http://nbn-resolving.de/urn:nbn:de:bvb:29-opus4-83179
(Techreport)
Vaas S., Ulbrich P., Reichenbach M., Fey D.:
The Best of Both: High-performance and Deterministic Real-Time Executive by Application-Specific Multi-Core SoCs
Conference on Design and Architectures for Signal and Image Processing (DASIP '17) (Dresden, 27. September 2017 - 29. September 2017)
In: Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP '17), Los Alamitos, CA: 2017
DOI: 10.1109/DASIP.2017.8122107
Hofmann J., Fey D., Riedmann M., Eitzinger J., Hager G., Wellein G.:
Performance analysis of the Kahan-enhanced scalar product on current multi-core and many-core processors
In: Concurrency and Computation-Practice & Experience 29 (2017)
ISSN: 1532-0626
DOI: 10.1002/cpe.3921
Biglari M., Fey D.:
A Non-Volatile Flip-Flop Using Memristive Voltage Divider
IEEE/ACM Design Automation and Test in Europe (DATE), Workshop on Emerging Memory Solutions - Technology, Manufacturing, Architectures, Design and Test (Lausanne, 31. März 2017 - 31. März 2017)
Wust D., Biglari M., Knödtel J., Reichenbach M., Söll C., Fey D.:
Prototyping Memristors in Digital Systems with an FPGA-Based Testing Environment
International Symposium on Power and Timing Modeling, Optimization and Simulation (Thessaloniki, 25. September 2017 - 27. September 2017)
In: Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017 27th International Symposium on 2017
DOI: 10.1109/PATMOS.2017.8106978
URL: http://ieeexplore.ieee.org/document/8106978/
Kohl J., Bauer W., Bäsig J., Rübesam S., Fey D.:
Processor Error Detection Capabilities of Random Programs
Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (Lübeck, Germany)
In: Tagungsband TuZ 2017 2017
Lieske T., Pfundt B., Vaas S., Reichenbach M., Fey D.:
System on Chip Generation for Multi-Sensor and Sensor Fusion Applications
17th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (Island of Samos, Greece)
In: Proceedings of the 17th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2017
DOI: 10.1109/SAMOS.2017.8344607
URL: https://ieeexplore.ieee.org/document/8344607/
Rachuj S., Hartmann C., Fey D.:
Evaluation of a Processor Simulator Exemplified by a Radar Processing Algorithm
ARCS 2017: 30th International Conference on Architecture of Computing Systems (Wien)
In: Workshop Proceedings, Wien: 2017
Reichenbach M., Holzinger P., Häublein K., Lieske T., Blinzer P., Fey D.:
LibHSA: One Step Towards Mastering the Era of Heterogeneous Hardware Accelerators using FPGAs
2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)
DOI: 10.1109/DASIP.2017.8122108
Ditter A., Schönwetter D., Kuzmin A., Fey D., Aizinger V.:
Memory Analysis and Performance Modeling for HPC Applications on Embedded Hardware via Instruction Accurate Simulation
Federated Conference on Software Development and Object Technologies, SDOT 2015 (Žilina, 19. November 2015 - 20. November 2015)
In: Proceedings of the 2015 Federated Conference on Software Development and Object Technologies, Cham: 2017
DOI: 10.1007/978-3-319-46535-7_2
Biglari M., Fey D.:
Memristive Voltage Divider: A Bipolar ReRAM-based Unit for Non-Volatile Flip-Flops
The International Symposium on Memory Systems (MEMSYS) (Alexandria, VA, 2. Oktober 2017 - 5. Oktober 2017)
In: MEMSYS'17 Proceedings of the International Symposium on Memory Systems 2017
DOI: 10.1145/3132402.3132432
URL: https://dl.acm.org/citation.cfm?id=3132432
Ditter A., Graf G., Fey D.:
Fe2vCl2: From Bare Metal to High Performance Computing on Virtual Clusters and Cloud Infrastructure
4th Workshop on CrossCloud Infrastructures and Platforms, CrossCloud 2017 (Belgrad, 23. April 2017)
In: Proceedings of the 4th Workshop on CrossCloud Infrastructures & Platforms, New York, NY, USA: 2017
DOI: 10.1145/3069383.3069386
URL: http://doi.acm.org/10.1145/3069383.3069386
Hartmann C., Häublein K., Pfundt B., Reichenbach M., Fey D.:
An Image Processing Operator Language for Design and Synthesis of Smart Camera Architectures
Parallel-Algorithmen und Rechnerstrukturen (Hagen)
In: Mitteilungen - Gesellschaft für Informatik e.V. 2017
Wust D., Söll C., Fey D.:
A fast general purpose CPU utilizing signed-digit encoding and multi-bit memristors
HiPEAC Workshop on Memristor Technology, Design, Automation and Computing
Hofmann J., Hager G., Wellein G., Fey D.:
An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors
32nd International Conference on High Performance Computing: ISC High Performance 2017 (Frankfurt)
In: High Performance Computing. ISC 2017. Lecture Notes in Computer Science, vol 10266, Cham: 2017
DOI: 10.1007/978-3-319-58667-0_16
Reichenbach M., Kasparek M., Häublein K., Bauer JN., Alawieh M., Fey D.:
Fast heterogeneous computing architectures for smart antennas
In: Journal of Systems Architecture (2017)
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2016.11.004
Widerspick C., Fey D., Hartmann C.:
Estimation of Time Behaviour of Selected Autonomous Driving Algorithms using GPGPU-Sim
ARCS 2017: 30th International Conference on Architecture of Computing Systems (Wien)
In: Workshop Proceedings, Wien: 2017
Fey D., Hartmann C., Widerspick C.:
A Methodology to Estimate the Energy Consumption and Processing Time for Image Processing Algorithms in Advanced Driver Assistance Systems
ARCS 2017: 30th International Conference on Architecture of Computing Systems (Wien)
In: Workshop Proceedings, Wien: 2017
Kohl J., Bauer W., Bäsig J., Fey D.:
Evaluating a Simulation based PLC Processor Optimization
15th Annual Industrial Simulation Conference (Warsaw, Poland)
In: ISC 2017 2017
Lieske T., Uhring W., Dumas N., Leonard J., Fey D.:
Embedded Fluorescence Lifetime Determination for High Throughput Real-Time Droplet Sorting with Microfluidics
Conference on Design and Architectures for Signal and Image Processing (DASIP) (Dresden)
In: Proceedings of 2017 Conference on Design and Architectures for Signal and Image Processing (DASIP) 2017
DOI: 10.1109/DASIP.2017.8122129
Lieske T., Schuklin D., Hohnloser D., Reichenbach M., Pfundt B., Fey D., Weigel R.:
Smart Sensor Framework: A Pressure Sensor for Smart Home Applications
1. E|HOME-CENTER SYMPOSIUM (Nürnberg, 30. November 2016 - 1. Dezember 2016)
Richter F., Fey D., Hain S.:
FPGA-aware Transformations of LLVM-IR
The First International Conference on Advances in Signal, Image and Video Processing (Lisbon, 26. Juni 2016 - 30. Juni 2016)
In: The First International Conference on Advances in Signal, Image and Video Processing 2016
Open Access: http://thinkmind.org/index.php?view=article&articleid=signal_2016_1_40_80070
Lieske T., Reichenbach M., Ringlein B., Fey D.:
Dataflow Optimization for Programmable Embedded Image Preprocessing Accelerators
2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig) (Cancun, Mexico, 30. November 2016 - 2. Dezember 2016)
In: Proceedings of ReConFig' 16 2016
DOI: 10.1109/ReConFig.2016.7857161
URL: http://ieeexplore.ieee.org/document/7857161/
Vaas S., Reichenbach M., Hofmann J., Stadelmayer T., Fey D.:
Embedded Parallel Computing Accelerators for Smart Control Units of Frequency Converters
12th Workshop on Parallel Systems and Algorithms (PASA) (Nuremberg, 4. April 2016 - 7. April 2016)
In: ARCS 2016; 29th International Conference on Architecture of Computing Systems, Nuremberg, Germany: 2016
Schäfer F., Bakakeu Ngassam R., Kleinert B., Michl M., Fey D., Franke J.:
Designing an OPC UA based Ecosystem for Smarter Homes
Advanced Engineering Forum 19 (Nürnberg)
In: Advanced Engineering Forum 19 2016
Richter F., Fey D.:
Cellular Neural Networks for FPGAs with OpenCL
CNNA 2016; 15th International Workshop on Cellular Nanoscale Networks and their Applications (23-25 Aug. 2016)
In: CNNA 2016; 15th International Workshop on Cellular Nanoscale Networks and their Applications, Berlin, Offenbach: 2016
URL: http://ieeexplore.ieee.org/document/7827967/
Hannig F., Cardoso J., Fey D., Schröder-Preikschat W., Teich J.:
Architecture of computing systems – ARCS 2016: 29th international conference Nuremberg, Germany, April 4-7, 2016 Proceedings
Springer Verlag, 2016
ISBN: 9783319306940
DOI: 10.1007/978-3-319-30695-7
Schönwetter D., Ditter A., Aizinger V., Reuter B., Fey D.:
Cache Aware Instruction Accurate Simulation of a 3-D Coastal Ocean Model on Low Power Hardware
6th International Conference on Simulation and Modeling Methodologies, Technologies and Applications (Lisbon)
DOI: 10.5220/0006006501290137
(Conference report)
Kohl J., Demel C., Reichenbach M., Fey D.:
A SystemC Based Framework for Cycle Accurate Processor Simulation and Parameter Analysis
14th IFAC and IEEE Conference on Programmable Devices and Embedded Systems PDES 2015 (Brno/Lednice)
In: 14th IFAC and IEEE Conference on Programmable Devices and Embedded Systems PDES 2015, Brno: 2016
DOI: 10.1016/j.ifacol.2016.12.016
Pfundt B., Reichenbach M., Hartmann C., Häublein K., Fey D.:
Teaching Heterogeneous Computer Architectures Using Smart Camera Systems
Workshop on Microelectronics Education (Southampton)
In: Proceedings of the 11th Workshop on Microelectronics Education 2016
Fey D., Reichenbach M., Söll C., Biglari M., Röber J., Weigel R.:
Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits
The International Symposium on Memory Systems (MEMSYS) (Alexandria, VA, 3. Oktober 2016 - 6. Oktober 2016)
In: Proceedings of the Second International Symposium on Memory Systems 2016
DOI: 10.1145/2989081.2989124
URL: https://dl.acm.org/citation.cfm?id=2989124
Hofmann J., Fey D.:
An ECM-based Energy-efficiency Optimization Approach for Bandwidth-limited Streaming Kernels on Recent Intel Xeon Processors
4th International Workshop on Energy Efficient Supercomputing (Salt Lake City, UT, USA, 13. November 2016 - 18. November 2016)
In: Proceedings of the 4th International Workshop on Energy Efficient Supercomputing 2016
DOI: 10.1109/E2SC.2016.16
Vaas S., Reichenbach M., Fey D.:
An Application-Specific Instruction Set Processor for Power Quality Monitoring
23th Reconfigurable Architectures Workshop (RAW) (Chicago, 23. Mai 2016 - 27. Mai 2016)
In: Parallel and Distributed Processing Symposium Workshop (IPDPSW) 2016
DOI: 10.1109/IPDPSW.2016.143
Hofmann J., Fey D., Eitzinger J., Hager G., Wellein G.:
Analysis of Intel's Haswell Microarchitecture Using the ECM Model and Microbenchmarks
29th International Conference on Architecture of Computing Systems (Nuremberg)
In: Architecture of Computing Systems -- ARCS 2016: 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings, Cham: 2016
DOI: 10.1007/978-3-319-30695-7_16
Hofmann J., Fey D., Eitzinger J., Hager G., Wellein G.:
Analysis of intel’s haswell microarchitecture using the ECM model and microbenchmarks
Springer Verlag, 2016
ISBN: 9783319306940
DOI: 10.1007/978-3-319-30695-7_16
Vaas S., Reichenbach M., Margull U., Fey D.:
The R2-D2 Toolchain - Automated Porting of Safety-Critical Applications to FPGAs
2016 International Conference on ReConFigurable Computing and FPGAs (Cancun, 30. November 2016 - 2. Dezember 2016)
In: Proceedings of ReConFig' 16 2016
DOI: 10.1109/ReConFig.2016.7857192
URL: http://ieeexplore.ieee.org/document/7857192/
Richter-Gottfried F., Kreutzer P., Ditter A., Schneider M., Fey D.:
C++ Classes and Templates for OpenCL Kernels with PATOS
4th International Workshop on OpenCL (Wien, 19. April 2016 - 21. April 2016)
In: ACM (Hrsg.): Proceedings of the 4th International Workshop on OpenCL, New York, NY, USA: 2016
DOI: 10.1145/2909437.2909462
URL: http://dl.acm.org/citation.cfm?doid=2909437.2909462
Hofmann J., Fey D., Riedman M., Eitzinger J., Hager G., Wellein G.:
Performance analysis of the Kahan-enhanced scalar product on current multi-corecore and many-core processors
In: Concurrency and Computation-Practice & Experience 28 (2016)
ISSN: 1532-0626
DOI: 10.1002/cpe.3921
Fey D., Reichenbach M., Söll C., Weigel R.:
Evaluating Signed-digit Arithmetic Circuits using Multi-level storing Memristors
HIPEAC Workshop on Memristor Technology, Design, Automation and Computing (Prague)
Bauer W., Kohl J., Bäsig J., Rübesam S., Fey D.:
Generation of Executable Runtime Constrained Random Programs Functional Processor Verification
The European Simulation and Modelling Conferences (Gran Canaria, Spain, 26. Oktober 2016 - 28. Oktober 2016)
In: ESM 2016 2016
Hannig F., Cardoso JMP., Pionteck T., Fey D., Schröder-Preikschat W., Teich J. (Hrsg.):
Proceedings of the 29th International Conference on Architecture of Computing Systems (ARCS)
Berlin; Heidelberg: 2016
(Lecture Notes in Computer Science (LNCS), Bd. 9637)
ISBN: 978-3-319-30694-0
DOI: 10.1007/978-3-319-30695-7
Schönwetter D., Ditter A., Kleinert B., Hendricks A., Aizinger V., Fey D.:
Virtualization Guided Tsunami and Storm Surge Simulations for Low Power Architectures
DOI: 10.1007/978-3-319-31295-8_7
Häublein K., Hartmann C., Reichenbach M., Fey D.:
Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks
ARC 2016 - International Symposium on Applied Reconfigurable Computing (Mangaratiba, Brazil, 22. März 2016 - 24. März 2016)
In: Applied Reconfigurable Computing, Mangaratiba: 2016
DOI: 10.1007/978-3-319-30481-6
Hartmann C., Häublein K., Reichenbach M., Fey D.:
IPAS: a design framework for analysis, synthesis and optimization of image processing applications for heterogenous computing architectures
In: Journal of Real-Time Image Processing (2016), S. 1-16
ISSN: 1861-8200
DOI: 10.1007/s11554-016-0587-x
URL: http://link.springer.com/article/10.1007/s11554-016-0587-x
Schönwetter D., Ditter A., Fey D., Mader R.:
Improving instruction accurate simulation for parallel automotive applications
11th IEEE International Symposium on Industrial Embedded Systems, SIES 2016 ([], 23. Mai 2016 - 25. Mai 2016)
In: 11th IEEE Symposium on Industrial Embedded Systems, SIES 2016, Krakow, Poland, May 23-25, 2016 2016
DOI: 10.1109/SIES.2016.7509432
Häublein K., Reichenbach M., Reiche O., Özkan MA., Fey D., Hannig F., Teich J.:
Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures
16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (Island of Samos, 18. Juni 2016 - 21. Juni 2016)
In: Proceedings of the 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2016
DOI: 10.1109/SAMOS.2016.7818350
Kleinert B., Schäfer F., Weiß S., Bakakeu Ngassam R., Fey D.:
Hardware-Software Co-Simulation of Self-Organizing Smart Home Networks: Who am I and where are the others?
Kleinert B., Weiß S., Schäfer F., Bakakeu Ngassam R., Fey D.:
Adaptive Synchronization Interface for Hardware-Software Co-Simulation based on SystemC and QEMU
Simutools: 9th EAI International Conference on Simulation Tools and Techniques
Reiche O., Häublein K., Reichenbach M., Schmid M., Hannig F., Teich J., Fey D.:
Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge
In: Journal of Systems Architecture 61 (2015), S. 646-658
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2015.09.004
URL: https://www12.cs.fau.de/downloads/reiche/publications/RHRSHTF15.pdf
Herglotz C., Seiler J., Kaup A., Hendricks A., Reichenbach M., Fey D.:
Estimation of Non-functional Properties for Embedded Hardware with Application to Image Processing
22nd Reconfigurable Architectures Workshop (RAW) on the 29th Annual International Parallel & Distributed Processing Symposium (IPDPS) (Hyderabad, 25. Mai 2015 - 29. Mai 2015)
DOI: 10.1109/IPDPSW.2015.58
Pfundt B., Reichenbach M., Fey D., Söll C.:
Novel Image Processing Architecture for 3D Integrated Circuits
Parallel -Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS) (Potsdam)
Hofmann J., Eitzinger J., Fey D.:
Execution-Cache-Memory Performance Model: Introduction and Validation
(2015)
URL: https://arxiv.org/abs/1509.03118
(Techreport)
Hannig F., Fey D., Lokhmotov A. (Hrsg.):
Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015)
2015
Open Access: http://arxiv.org/abs/1502.07241
URL: http://arxiv.org/abs/1502.07241
Hofmann J., Fey D., Eitzinger J., Hager G., Wellein G.:
Performance analysis of the Kahan-enhanced scalar product on current multicore processors
the 11th International Conference on Parallel Processing and Applied Mathematics (Krakow, Poland)
In: Accepted for PPAM 2015 2015
URL: http://arxiv.org/abs/1505.02586
Limmer S., Ditter A., Fey D., Pruksch M., Braun C., Drescher F., Beißer-Dresel M.:
Test@Cloud - A Platform for Test Execution in the Cloud
Parallel -Algorithmen, -Rechnerstrukturen und -Systemsoftware (Potsdam)
In: Parallel-Algorithmen und Rechnerstrukturen 2015
Reichenbach M., Kasparek M., Alawieh M., Häublein K., Fey D.:
Real-Time Correlation for Locating Systems Utilizing Heterogeneous Computing Architectures
Conference on Design & Architectures for Signal & Image Processing (Cracow)
In: Proceedings of the 2015 Conference on Design & Architectures for Signal & Image Processing 2015
Reiche O., Häublein K., Reichenbach M., Hannig F., Teich J., Fey D.:
Automatic Optimization of Hardware Accelerators for Image Processing
DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) (Grenoble, 13. März 2015 - 13. März 2015)
In: Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) 2015
URL: http://arxiv.org/abs/1502.07448
Hartmann C., Yupatova A., Reichenbach M., Fey D., German R.:
A Holistic Approach for Modeling and Synthesis of Image Processing Applications for Heterogeneous Computing Architectures
HIS Workshop. Design, Automation & Test in Europe (DATE) (Grenoble)
In: Proceedings of HIS Workshop. Design, Automation & Test in Europe (DATE) 2015
Ditter A., Schaffert R., Fey D., Schön T., Gruber R.:
Multi-GPU Based Evaluation and Analysis of Prehistoric Ice Cores Using OpenCL
International Conference on Imaging Systems and Techniques (Macau, China, 16. September 2015 - 18. September 2015)
In: IST 2015 Proceedings 2015
DOI: 10.1109/IST.2015.7294561
Reichenbach M., Lieske T., Vaas S., Häublein K., Fey D.:
FAUPU - A Design Framework for the Development of Programmable Image Processing Architectures
2015 International Conference on ReConFigurable Computing and FPGAs (Mayan Riveria, Mexico)
In: Proceedings of ReConFig' 15 2015
DOI: 10.1109/ReConFig.2015.7393309
Schönwetter D., Ditter A., Kleinert B., Hendricks A., Aizinger V., Köstler H., Fey D.:
Tsunami and Storm Surge Simulation Using Low Power Architectures - Concept and Evaluation
5th International Conference on Simulation and Modeling Methodologies, Technologies and Applications (Colmar, 21. Juli 2015 - 23. Juli 2015)
In: Proceedings of the 5th International Conference on Simulation and Modeling Methodologies, Technologies and Applications, Colmar, Alsace, France: 2015
DOI: 10.5220/0005566603770382
Bürner J., Ditter A., Fey D., Franke J.:
SmartEco: An Integrated Solution from Load Balancing between the Grid and Consumers to Local Energy Efficiency
8th International Conference on Utility and Cloud Computing (Limassol, 7. Dezember 2016 - 10. Dezember 2015)
In: IEEE (Hrsg.): IEEE/ACM 8th International Conference on Utility and Cloud Computing (UCC) 2015
Schönwetter D., Veldema R., Fey D.:
FREACSIM - A Framework for Creating and Simulating Real-Time Capable Network on Chip Systems and Applications
8th EAI International Conference on Simulation Tools and Techniques (SIMUTOOLS'16) (Athens, Greece, 24. August 2015 - 26. August 2015)
In: Theodoropoulos, Georgios ; Tan Soon Huat, Gary ; Szabo, Claudia (Hrsg.): Proceedings of the 8th EAI International Conference on Simulation Tools and Techniques (SIMUTOOLS'16), European Union Digital Library: 2015
DOI: 10.4108/eai.24-8-2015.2260960
URL: http://eudl.eu/doi/10.4108/eai.24-8-2015.2260960
Richter F., Ditter A., Fey D.:
OpenCL 2.0 for FPGAs using OCLAcc
Second International Workshop on FPGAs for Software Programmers (FSP 2015) (London)
In: Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015) 2015
URL: http://arxiv.org/abs/1508.07977
Reichenbach M., Pfundt B., Fey D.:
Framework for Parameter Analysis of FPGA-based Image Processing Architectures
International Conference on Systems, Architectures, MOdeling and Simulation (SAMOS) (Samos)
In: Proceedings of International Conference on Systems, Architectures, MOdeling and Simulation (SAMOS) 2015
Brossog M., Hartmann C., Kohl J., Merhof J., Reichenbach M., Fey D., Franke J.:
Prozessflexible Steuerung von Industrierobotern
In: wt Werkstattstechnik - Online 104 (2014), S. 535-540
ISSN: 1436-4980
URL: http://www.werkstattstechnik.de/
Berschneider S., Herglotz C., Reichenbach M., Fey D., Kaup A.:
Estimating Video Decoding Energies And Processing Times Utilizing Virtual Hardware
3PMCES Workshop. Design, Automation & Test in Europe (DATE) (Dresden, 24. März 2014 - 28. März 2014)
Ditter A., Fey D., Schön T., Steven O.:
On the Way to Big Data Applications in Industrial Computed Tomography
3rd International Congress on Big Data (Anchorage, 27. Juni 2014 - 2. Juli 2014)
In: Proceedings of BigData Congress 2014, Los Alamitos, CA, USA: 2014
DOI: 10.1109/BigData.Congress.2014.125
Richter F., Fey D.:
OCLAcc: An Open-source Generator for Configurable Logic Block based Accelerators
Embedded World Conference (Nuremberg)
In: Embedded World Conference Proceedings, Haar: 2014
Ditter A., Fey D.:
Security Aspects of Cloud Computing - Trusted Cloud in Cloud4E
ITI Symposium (Dresden)
In: Conference Proceedings of the 17th ITI Symposium 2014
Häublein K., Reichenbach M., Fey D.:
Fast and Generic Hardware Architecture for Stereo Block Matching Applications on Embedded Systems
2014 International Conference on ReConFigurable Computing and FPGAs (Cancun, Mexico, 8. Dezember 2014 - 10. Dezember 2014)
In: Proceedings of ReConFig' 14 2014
DOI: 10.1109/ReConFig.2014.7032518
Reichenbach M., Pfundt B., Fey D.:
Designing and Manufacturing of Real Embedded Multi-Core CPUs: A Holistic Teaching Approach in Computer Architecture
Workshop on Microelectronics Education (Tallin, Estonia, 14. Mai 2014 - 16. Mai 2014)
In: Proceedings of the Tenth Workshop on Microelectronics Education 2014
DOI: 10.1109/EWME.2014.6877428
Ditter A., Pruksch M., Limmer S., Fey D.:
Testen in der Cloud - Automatisiertes Testen in virtualisierten Umgebungen
In: Elektrotechnik Juli/August (2013), S. 62-63
ISSN: 1619-9405
URL: http://files.vogel.de/vogelonline/vogelonline/issues/epaperarchiv/elektrotechnik_0713/index.html
Ditter A., Limmer S., Fey D.:
i3sched Ein OpenNebula Scheduler für die Oracle Grid Engine
Grid-, Cloud und Big-Data Technologien für Systementwurf und -analyse (Dresden)
In: Grid-, Cloud und Big-Data Technologien für Systementwurf und -analyse 2013
Reichenbach M., Seidler R., Pfundt B., Fey D.:
Fast image processing for optical metrology utilizing heterogeneous computer architectures
In: Computers & Electrical Engineering (2013)
ISSN: 0045-7906
DOI: 10.1016/j.compeleceng.2013.09.008
URL: http://www.sciencedirect.com/science/article/pii/S0045790613002474
Schönwetter D., Sieh V., Fey D.:
Porting an Engine Control Application to a Virtual Environment by using an Open Source Real Time Operating System
Embedded World Conference (Nuremberg)
In: Embedded World Conference Proceedings, Haar: 2013
Pfundt B., Reichenbach M., Eskofier B., Fey D.:
Smart Sensor Architectures for Embedded Biosignal Analysis
Design & Architectures for Signal & Image Processing (Cagliari, 8. Oktober 2013 - 10. Oktober 2013)
In: Proceedings of the 2013 Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy: 2013
Ditter A., Fey D., Schön T., Luxa M., Gruber R.:
The Impact of H.264/AVC on Compression and Non-Destructive Evaluation of Piston Data in Industrial Computed Tomography
International Conference on Imaging Systems and Techniques (Peking, China, 22. Oktober 2013 - 23. Oktober 2013)
In: IST 2013 Proceedings 2013
DOI: 10.1109/IST.2013.6729699
Hofmann J., Limmer S., Fey D.:
Performance Investigations of Genetic Algorithms on Graphics Cards
In: Swarm and Evolutionary Computation (2013), S. 33-47
ISSN: 2210-6502
DOI: 10.1016/j.swevo.2013.04.003
URL: http://www.sciencedirect.com/science/article/pii/S2210650213000187
Ditter A., Limmer S., Fey D., Pruksch M.:
Modellzentrierter Test in virtualisierten Testumgebungen
April (2013), S. 3-4
URL: http://www.cluster-ma.de/fileadmin/user_upload/bilder/newsletter2013/newsletter2013_04/mechatroniknews_april_2013.pdf
(online publication)
Hofmann J., Fey D.:
Fast Evolutionary Algorithms: Comparing High Performance Capabilities of CPUs and GPUs
Parallel-Algorithmen und Rechnerstrukturen (Erlangen)
In: Mitteilungen - Gesellschaft für Informatik e.V. 2013
Limmer S., Fey D., Jahn J.:
GPU implementation of a multiobjective search algorithm
In: Positivity 16 (2012), S. 397-404
ISSN: 1385-1292
DOI: 10.1007/s11117-012-0156-x
Richter F., Schmidt M., Fey D.:
A Configurable VHDL Template for Parallelization of 3D Stencil Codes on FPGAs
ERSA'12 (Las Vegas)
In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas: 2012
Reichenbach M., Schmidt M., Pfundt B., Fey D.:
A New Virtual Hardware Laboratory for Remote FPGA Experiments on Real Hardware
EEE 2011 (Las Vegas)
In: Proceedings of the 2011 International Conference on E-Learning, E-Business, Enterprise Information Systems, &E-Goverment, Las Vegas: 2011
Sand M., Sieh V., Fey D.:
Nano-technology aware investigations on fault-masking techniques in the presence of high fault probabilities
2010 International Conference on High Performance Computing and Simulation (HPCS) (Caen, France, 28. Juni 2010 - 2. Juli 2010)
In: Proceedings of the 2010 International Conference on High Performance Computing and Simulation (HPCS) 2010
DOI: 10.1109/HPCS.2010.5547139