Farhad Ebrahimiazandaryani

Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Wissenschaftliche Mitarbeitende

Kontakt

E-Mail: farhad.ebrahimiazandaryani@fau.de

Profile Info

Digital Design Engineer with over six years of hands-on experience in FPGA and RTL design, specializing in SoC development, RISC-V processors, hardware acceleration, HW/SW co-design, and embedded systems/Linux development. Experienced across the complete development lifecycle, including architecture definition, RTL design, simulation, synthesis, implementation, timing analysis, verification, debugging, validation, and system integration. Proven expertise in developing FPGA-based SoC platforms, custom processors, and high-performance computing architectures using Xilinx Zynq and UltraScale+ devices for research and industrial applications.

Area of Expertise

FPGA and RTL Design
Low-Power Digital Design
Reconfigurable Computing
Hardware/Software Co-Design
SoC Architecture and Development
Custom RISC-V processor design
Hardware Accelerator Development
Embedded Systems and Linux (PetaLinux)
Computer Architecture and Microarchitecture

Teaching

Architecture of Supercomputers (ArchSup) Winter 2022/23 - ongoing
Computer Architecture for Medical Applications (CAMA) Summer 2023 - ongoing

Supervised M.Sc. | BSc Thesis

If you're a bachelor's or master's student looking for a thesis topic and your research background aligns with mine, feel free to reach out—I'd be happy to discuss potential opportunities with you!

Publications

F. EbrahimiAzandaryani , M. Kupfer and D. Fey, " Silicon-Based Evaluation of CSD Arithmetic in a RISC-V Processor Using Open-Source ASIC Flow, " 2026 IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, 2026, pp. 1699-1703.
A. Abdelhafez, F. EbrahimiAzandaryani , M. Bianconi and D. Fey, “ FPGA Implementation of a Real-Time Application Based on RISC-V Cores ” 2025 IEEE 22nd International Multi-Conference on Systems, Signals & Devices (SSD), Monastir, Tunisia, 2025, pp. 1174-1179.
F. EbrahimiAzandaryani and D. Fey, “ CSD-Driven Speedup in RISC-V Processor ” In: Lorandel, J., Kamaleldin, A. (eds) Design and Architecture for Signal and Image Processing. DASIP 2025. Lecture Notes in Computer Science, vol 15569. Springer, Cham.
F. EbrahimiAzandaryani and D. Fey, “ ExTern: Boosting RISC-V core performance using ternary encoding ” Microprocessors and Microsystems , volume 107(2024), https://doi.org/10.1016/j.micpro.2024.105058.
F. EbrahimiAzandaryani , O. Akbari, M. Kamal, A. Afzali-Kusha, and M. Pedram, “ Accuracy configurable adders with negligible delay overhead in exact operating mode ” ACM Trans. Des. Autom. Electron. Syst ., vol. 28, no. 1, pp. 1–14, Jan. 2023.
F. EbrahimiAzandaryani , O. Akbari, M. Kamal, A. Afzali-Kusha, and M. Pedram, “ Block-based carry speculative approximate adder for energy-efficient applications, ”IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 67, no. 1, pp. 137–141, Jan. 2019.